Delay lines are used within integrated circuits for a wide variety of applications, such as for adjusting or modifying the phase alignment between two signals. In one application, delay lines are used for aligning clock signals for capturing data within a data valid window. For example, certain types of memory devices generate a clock strobe signal having edges that are aligned with changes in the read data.
A double data rate (DDR) dynamic random access memory (DRAM) transfers data on each rising and falling edge of the clock strobe signal. A DDR DRAM therefore transfers two data words per clock cycle. A memory controller is often used to coordinate the transfer of data to and from a memory device, such a DDR DRAM. The memory controller provides a local clock signal to the memory device for synchronizing read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the memory controller. The memory controller uses the clock strobe signal for determining when the read data is valid and can therefore be captured. The times at which the read data is captured are preferably synchronized to the clock strobe signal so as to capture the read data in the middle of the valid data window.
The clock strobe signal is therefore typically delayed through a delay line such that its transitions line up with the middle of the data valid window. The amount of delay provided by the delay line can vary with process, voltage and temperature changes. Therefore, the delay line is preferable programmable such that the settings of the delay line can be adjusted to make the propagation delay through the delay line a proper duration relative to a reference clock. An algorithm is used to determine the correct setting of the delay line, and this algorithm is continually executed to keep the delay line calibrated to an optimum value with changes in voltage and temperature.
A typical calibration circuit uses an analog or digital delay lock loop (DLL) for calibrating the delay setting to the reference clock. Current DLL circuits include a slave delay line having multiple, cascaded delay cells which, when set properly, have a total propagation delay that is equal to the period of the reference clock. A circuit compares the phases of the rising and falling edges of the reference clock with the phase of the output from the DLL and then adjusts the delay setting in the DLL so that the delay is equal to the period of the reference clock. At this point, the delay through each slave delay cell equals a desired fraction of the reference clock period. The delay setting for the slave delay line can then be used to delay the clock strobe signal by the desired fractional amount of the reference clock.
These types of calibration circuits usually require several iterations in order to lock in on a proper delay setting. After each iteration, a binary search of delay values or another type of algorithm is used to determine the delay setting for the next iteration of the calibration attempt. If a large number of iterations is required, this can adversely affect the efficiency of the calibration circuit. Another disadvantage of a binary search algorithm and potentially other algorithms is that it is possible to overshoot the desired delay line setting. If the slave delay line in the calibration circuit is used within a ring oscillator, overshooting the delay line setting can temporarily create a very high frequency system that makes meeting design timing difficult. In addition, multiple delay cells are required, thus adding area to the design. A further disadvantage is that a fixed number of delay cells causes the single cell delay value to be a fixed fractional value of the reference clock, thus making the circuit unable to lock on to other fractional values of the reference clock.
Improved methods and apparatus are therefore desired for calibrating a delay line to a reference clock.